1. Field of the Invention
The present invention pertains generally to the field of radio frequency power transistors, and more specifically to methods and apparatus for output impedance matching of an LDMOS power transistor device.
2. Background
The use of radio frequency (RF) amplifiers, for example, in wireless communication networks, is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services (PCS), the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz (GHz) frequencies. At such high frequencies, LDMOS transistors have been preferred for RF power amplification devices, e.g., in antenna base stations.
In a typical deployment, an LDMOS RF power transistor device generally comprises a plurality of electrodes formed on a silicon die, each electrode comprising a plurality of interdigitated transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals for each electrode. The die is attached, by a known eutectic die attach process, atop a metallic (source) substrate, which is itself mounted to a metal flange serving as both a heat sink and a ground reference. Respective input (gate) and output (drain) lead frames are attached to the sides of the flange, electrically isolated from the metal (source) substrate, wherein the input and output lead frames are coupled to the respective electrode input and output terminals on the silicon die by multiple wires (i.e., bonded to the respective terminals and lead frames).
Impedance matching the input and output electrode terminals to the respective input and output lead frames is crucial to proper operation of the amplifier device, especially at high operating frequencies.
By way of illustration, FIG. 1 shows a simplified electrical schematic of an unmatched LDMOS device, having an input (gate) lead 12, an output (drain) lead 14 and a source 16 through an underlying substrate. Transmission inductance through the input path, e.g., a plurality of bond wires connecting the input lead 12 to the common input terminal of the respective transistor fingers, is represented by inductance 18. Output inductance through the output path, e.g., a plurality of bond wires connecting the common output terminal of the respective transistors to the output lead 14, is represented by inductance 20.
FIG. 2 shows a known (matched) LDMOS power transistor device 40. The device 40 includes an input (gate) lead 42, output (drain) lead 44 and metallic (source) substrate 47 attached to a mounting flange 45. A first plurality of wires 48 couple the input lead 42 to a first terminal of an input matching capacitor 46. A second terminal of the input matching capacitor 46 is coupled to ground (i.e., flange 45). A second plurality of wires 52 couple the first terminal of matching capacitor 46 to the respective input terminals 49 of a plurality of interdigitated electrodes 51 formed on a semiconductor die 50 attached to the metallic substrate 47. By proper selection of the matching capacitor 46 and the series inductance of wires 48 and 52, the input impedance between the input lead 42 and electrode input terminals 49 can be effectively matched.
Respective output terminals 53 of the electrodes are coupled to the output lead 44 by a third plurality of wires 54. In order to impedance match the output of the device, a shunt inductance is used. Towards this end, the output lead 44 is coupled to a first terminal of a DC blocking capacitor 58 (i.e., an AC short) by a fourth plurality of wires 60, the blocking capacitor 58 having a substantially higher value than the input matching capacitor 46. FIG. 3 shows a schematic circuit representation of the device of FIG. 2, wherein the transmission inductance through the respective pluralities of wires is designated by the corresponding reference numbers of the wires in FIG. 2.
For "lower frequency" applications, e.g., 1500 MHz, the LDMOS device 40 of FIG. 2 may be adequately controlled, but at higher frequencies, e.g., 2 GHz, effective control of the device becomes difficult due to the relatively large series inductance generated through wires 54 to the shunt inductance 60. Further, because there is limited physical space on the electrode output terminals 53, the number of wires 54 connecting the plurality of electrodes 51 to the output lead 44 is thereby limited.
Thus, it would be desirable to provide an LDMOS RF power transistor device in which output matching at relatively high frequencies (e.g., GHz) can be more easily accomplished.